How Much Power Can An Fpga Draw

Introduction

As transistor technology quickly shrinks toward the vanishing bespeak, embedded devices are taking over the marketplace. I of the key challenges of designing an embedded electronic device is maintaining reasonable ability consumption in social club to maximize battery life. For blueprint engineers wanting to combine the functionality of a microcontroller with their own "special sauce" logic, a standard off-the-shelf microcontroller plus Field Programmable Gate Array (FPGA) combination has long been the preferred option.

Despite the ease of utilise and availability of FPGAs, they are notoriously ability hungry and can quickly overwhelm the power upkeep of an embedded organization. Transistor leakage currents atomic number 82 to loftier static ability consumption that is independent of logic implementation within the FPGA. This is just unacceptable for designers whose products have strict power requirements. Awarding Specific Integrated Circuits (ASICs), on the other paw, allow full customizability and utilize low-power standard cells, achieving much better functioning than possible with a similarly configured FPGA. Withal, ASIC design and production can be prohibitively expensive for smaller companies or those producing only a limited quantity of product. Past leveraging the newly developed Metal Programmable Cell Fabric (MPCF) engineering science, Customizable Atmel Processors (CAP) customizable microcontrollers can dramatically reduce ability consumption while allowing engineers to implement their logic in a single flake that carries the full functionality of a microcontroller plus FPGA system.

The FPGA Power Trouble and CAP

While an attractive option for prototyping and emulation, FPGAs mostly are not capable of achieving the same level of operation every bit client-specified ASICs. With FPGAs, the benefit of re-programmability comes with the disadvantage of inefficiency. Logic utilization tends to be low due to place-and-route constraints, and unused transistors do nil but consume extra power. Long signal paths and inefficient clock-trees add to the power hungry nature of FPGAs—a necessary evil if ane requires the ability to tweak their logic. Thus, FPGAs are natural choices for new production development. Nevertheless, they are less than ideal once the logic is finalized and power issues become relevant.

While offering much better power performance, ASICs have high upfront NRE costs and, depending upon complexity, right-first-time adventure. Atmel'due south customizable microcontrollers offer an alternative to a microcontroller-plus-FPGA combination or an ASIC. A CAP MCU is basically an ARM-based system-on-fleck with a fixed selection of peripherals and a Metal Programmable (MP) cake. The ARM core and peripherals on the CAP MCU constitute a fully functional, fully verified microcontroller, then run a risk is greatly reduced.

The MP block is based on Atmel's newly developed MPCF cell library with routing densities comparable to those of standard prison cell ASIC libraries. MPCF significantly reduces the number of mask sets necessary for production—the most costly component of an ASIC NRE budget. Information technology achieves nearly the same logic densities as comparable ASIC designs and drives down ability consumption to within ten to 15% of full custom ASICs.

When compared to FPGAs, the power saved by using CAP is considerable: designers volition run across over a 95% reduction in static ability, and nearly a 70% decrease in dynamic power. This power efficiency, coupled with CAP'south low NRE price in comparison to ASICs presents a very attractive alternative to microcontroller-plus-FPGA designs. This paper proposes a method for evaluating the power consumption of FPGAs and customizable MCUs.

Hardware Used

An ARM7-based CAP7 with 450k ASIC equivalent gates was tested on a specially made test board supporting JTAG advice for manipulating the processor while running. The Xylo-50 evolution board (www.KNJN.com) with a 500k gate (125k ASIC-equivalent gate) Xilinx Spartan 3-East XCS500E FPGA and a Philips LPC2138 ARM7 was used to test the FPGA-plus-MCU implementation. The smaller size of the Spartan FPGA would be expected to give it a power consumption advantage over the CAP customizable MCU. The Xylo-Fifty board likewise has a USB interface used to load the FPGA boot configuration PROM and for manipulating the ARM. Figure one compares the architecture of the CAP7 with that of the Xylo-L board.

Effigy one: Comparing the architectures of CAP7 and the Xylo-L board. The MPLIB in CAP7 takes the place of an FPGA.

Both the CAP7 MCU and the Xilinx FPGA crave multiple voltage sources. However, the crucial power rail to monitor is the core or internal voltage source, every bit any internal logic draws on this supply. Both chips run at a nominal core voltage of 1.2V, facilitating directly comparison. A digital multimeter was hooked up in series with the power supply to monitor electric current consumption on the CAP7 test board, which includes a banana-plug jack for one.2V ability. All power on the Xylo-L lath is supplied past the 5V line on the USB jack. A trace was cut between the 1.2V regulator and the FPGA on the Xylo-L board and a multimeter connected to measure current consumption on the one.2V rail.

Initialization Procedures

To ensure a fair comparison, diverse factors need to be taken into account. All components of each board that could exist drawing any ability must be disabled in order to allow for a straight comparison between CAP7 and the FPGA. On the Xylo-50 lath this meant putting the Philips ARM7 into power-downwards way and ensuring a low default FPGA I/O state. Additionally, an onboard EEPROM had to be programmed to tell the USB controller to produce the necessary clock for the FPGA. The available clock frequencies were 12, 24, and 48 MHz.

Initialization of the CAP7 involved ensuring all I/O were low by default and setting upwards the required PLLs and oscillators. Information technology is particularly important to set MPIO81 low because information technology toggles the chip between platform and emulation modes. Emulation mode effectively shuts off all functionality except the ARM core, while Platform mode leaves the flake in its normal state. This was achieved by loading initialization lawmaking into the RAM on the CAP7 MCU, and stepping through it until in the proper state. CAP7 can be clocked as low equally 500Hz and equally high as 80MHz.

General Methodology

Static Power:
Static power is the power consumed past a device when information technology is not clocked. For the FPGA, a blank pattern was loaded into the kick PROM with no external clock lines specified. For CAP7, the master clock was set to run at 500Hz, the lowest possible value. Unfortunately the ARM7 cadre cannot be shut off and so the value measured is not a true static power measurement; however, 500Hz is low plenty that any extra current drawn by the ARM7 core would exist negligible. In whatever case, this would place the FPGA in the best light possible, giving an fifty-fifty more conservative estimate of CAP7's power in comparing.

Dynamic Power:
Dynamic power refers to the extra power a device consumes when it is clocked. To brand a valid dynamic ability comparison between the Spartan 3-E FPGA and CAP7, several peripherals, synthesized from a single RTL file, were implemented in both the Spartan FPGA and the CAP7 MP cake and clocked at a range of frequencies. The peripheralsincluded: 2 USARTs (Universal Synchronous Asynchronous Receiver Transmitters), an SPI (Serial Peripheral Interface), three Timer/Counters, and an ADC Controller (Analog to Digital Converter). To measure the power consumed by CAP7 using the aforementioned peripherals, clocks to the various peripherals were either enabled or disabled by manipulating the Power Management Controller.

The FPGA modules were instantiated one at a time with no I/O connections using Xilinx's ISE WebPack,. To keep things on an even playing field, the simply clocks supplied to each peripheral were the system and configuration clocks. Assay of the CAP7 design shows that the system and configuration clocks are the ii signals enabled when a peripheral is turned on in the Ability Management Controller.

For the Spartan 3-Eastward FPGA, current draw on the i.2V rail was measured for each of the peripheral combinations, and the static current was subtracted to produce a dynamic current value. For the CAP7 MCU, in order to eliminate the power consumption of the ARM7 core from the measurement, an "idle" current measurement was made with the chip clocked at full speed merely no peripherals enabled. This idle value was subtracted from the electric current measured with various peripheral combinations clocked.

Current measurements of the CAP7 device and the FPGA were made at 12, 24, and 48 MHz. with a carve up measurement of the CAP7 MCU at 80MHz. Due to the linear human relationship between clock frequency and power consumption, data collected for the Spartan 3-E FPGA could be used to extrapolate its power consumption at 80MHz and brand a direct comparing with CAP7 device. A value for percent ability reduction was calculated using the post-obit formula:

Results

Static Power:

At an internal core voltage of 1.256V, the Spartan 3-Due east consumed 10.71mA, resulting in a power consumption of 13.46mW. CAP7, on the other hand, drew only 274uA at the same core voltage, with a power consumption of 344uW, a 97% reduction over the FPGA. The 97% power decrease is really bourgeois, as it compares a FPGA with 125 ASIC-equivalent gates to a CAP7 MCU with 450k ASIC-equivalent gates. It would take about 1 meg FPGA gates to implement logic equivalent to that 450k-gate CAP7. Since static power consumption is direct related to gate-count, whatsoever FPGA larger than the one tested would consume more than power and thus boost power advantage of the CAP7 MCU.

Figure 2: Comparison the static power consumption of CAP7 and the Spartan 3-E FPGA.
CAP7 reduces static ability past 97%.

Dynamic Ability:

Eight different peripheral combinations were tested on both the Spartan 3-E FPGA and CAP7 customizable MCU. In each example, no data was transferred to or from the peripheral. Thus, the measurements indicate additional power consumed by clocking the peripherals. The combinations tested were as follows: ane USART, 2 USARTs, 1 SPI, one, two, and three Timer/Counters, one ADC Controller, and a combination of the higher up (two USARTs, one SPI, three Timer/Counters, and one ADC Controller). Figure 3 compares the power consumed by the Spartan 3-E and CAP7 at 80MHz.ⁱ

For both the FPGA and CAP7, the individual USART peripheral block consumed the near power, at 8.01mW for the Spartan 3-East and two.75mW for CAP7. Interestingly, while the Timer/Counter in CAP7 consumed the least power, at 1mW, the SPI was the least power hungry peripheral in the FPGA, at 4.10mW. Because of the dissimilar concrete nature of MPCF compared to FPGA logic cells, the low-level implementation of peripherals vary between the two.

On average, peripherals on CAP7 MCU consumed 68% less power than those in the Spartan 3-E FPGA. The largest power saving was observed for CAP7's ADC Controller, which posted an 84% reward over the FPGA. A combination of the four peripherals exhibited the lowest ratio of power advantage for CAP7, just even all the same CAP7 proved to reduce power past over 50%.

Table 1 tallies the results for both static and dynamic power comparisons.

Discussion

The MP block on CAP7 microcontroller holds a distinct power advantage when compared with the Spartan 3-E FPGA. Equally more peripherals are added, all the same, the disparity between the 2 becomes smaller. The well-optimized WebPack synthesis tool reuses the same logic between multiple peripheral instantiations. In CAP, each peripheral is instantiated as a singled-out block with no shared logic In the FPGA implementation the peripherals merely used the system and configuration clocks every bit inputs, and many peripheral I/O were left unconnected in the RTL. This led to optimizations during the synthesis of peripheral combinations where multiple instances of the same peripheral were used. For case, CAP'southward power reward for one Timer/Counter is 81%, a ratio that drops with further additions of Timer/Counters. Overall, the CAP7 reduced both the amass dynamic and static ability consumption by over 70% when compared to a Spartan 3-Due east FPGA-based pattern.

Conclusion

For design engineers who crave low-power, CAP customizable MCUs provide a low power alternative to an FPGA-plus-microcontroller solution and a low toll-low risk culling to a custom ASIC pattern. By saving over 95% in static power and almost 70% in dynamic power consumed by an FPGA, the Metal Programmable Prison cell Fabric (MPCF) in the CAP microcontrollers allows full customization and interface with an ARM core without fear of overwhelming a system's power or NRE budget.

¹Note that the FPGA ability at 80MHz was extrapolated from data gathered at 12, 24, and 48MHz.

About the Author: Koji Gardiner is a senior at Stanford University. He will receive his Bachelor of Science caste in Electrical Technology in 2008. He is currently applying to the co-terminal Master'south program at Stanford.